1. Field of the Invention
This disclosure generally relates to techniques for testing I/O subsystems in a computing device. More specifically, this disclosure relates to techniques for using a DMA engine to automatically validate DMA data paths and expose any latent bugs or throughput bottlenecks in an I/O subsystem.
2. Related Art
Recent advances in computational technology have led to improved processor capabilities, increased memory sizes, and increasingly sophisticated storage devices and peripherals. However, as the complexity of computer systems grows, comprehensively testing each component becomes difficult, and testing the interactions among multiple components even more so.
For instance, consider the process of developing and validating a high-performance I/O subsystem. A common challenge in validating an I/O subsystem in a lab is to create sufficient traffic to expose latent bugs or throughput bottlenecks, so that bug fixes or design modifications can be incorporated into the next version of a processor and/or chipset. Unfortunately, creating such traffic intensity can be difficult, because the needed leading-edge I/O devices and device drivers may also still be undergoing testing and may not yet be available. Earlier-generation devices can be used for testing purposes, but they may not generate enough traffic to adequately test a next-generation I/O subsystem. On the other hand, waiting until next-generation devices are available and fully supported potentially delays the discovery of some types of problems.
Hence, what is needed are techniques for validating an I/O subsystem without the above-described problems.